Study of the effects of SEU-induced faults on a pipeline protected microprocessor

Study of the effects of SEU-induced faults on a pipeline protected microprocessor

This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized...

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Bibliographic Details
Main Authors: E. Touloupis, James Flint, Vassilios Chouliaras, D.D. Ward
Format: Default Article
Published: 2007
Subjects:
Mechanical engineering not elsewhere classified
Distributed computing and systems software not elsewhere classified
Software engineering not elsewhere classified
Fault injection
Fault modeling and simulation
SEU
Soft error
Microprocessor test
Fault tolerance
Mechanical Engineering not elsewhere classified
Computer Software
Distributed Computing
Online Access:https://hdl.handle.net/2134/6133
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https://hdl.handle.net/2134/6133

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