A transmission line modelling VLSI processor processor designed with a novel electronic system level methodology
This paper discusses the development of a high performance, System-on-Chip (SoC) Transmission Line Modeling (TLM) accelerator designed using novel Electronic System-Level (ESL) flows, from reference C sources. The TLM processor includes a silicon implementation of the 32-bit subset of the IEEE 754 f...
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| Main Authors: | , , |
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| Format: | Default Conference proceeding |
| Published: |
2007
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| Subjects: | |
| Online Access: | https://hdl.handle.net/2134/6134 |
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