A system-on-chip vector multiprocessor for transmission line modelling acceleration
We discuss a configurable, System-on-Chip vector multiprocessor for accelerating the Transmission Line Modeling (TLM) algorithm with an architecture capable of exploiting the two primary forms of parallelism in the code, thread and data level parallelism. Theoretical results demonstrate an order of...
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| Main Authors: | , , , |
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| Format: | Default Conference proceeding |
| Published: |
2005
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| Subjects: | |
| Online Access: | https://hdl.handle.net/2134/6162 |
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