Hierarchical Cache Directory for CMP

As more processing cores are integrated into one chip and feature size continues to shrink, the average access la- tency for remote nodes using directory-based coherence protocol becomes higher, which greatly impacts system performance. Previous techniques such as data replication and data migration...

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Bibliographic Details
Published in:Journal of computer science and technology 2010-03, Vol.25 (2), p.246-256
Main Author: 郭松柳 王海霞 Senior Member, CCF 薛一波 李崇民 Student Member, CCF 汪乐升
Format: Article
Language:English
Subjects:
Artificial Intelligence
Asymptotic properties
Chemical-mechanical polishing
Chips
Communications traffic
Computer Science
Computer simulation
Data replication
Data Structures and Information Theory
Directories
Information Systems Applications (incl.Internet)
Mathematical models
Multiprocessing
Network latency
Nodes
Optimization techniques
Regular Paper
Simulation
Software Engineering
Theory of Computation
Tiles
一致性协议
性能要求
数据复制
特征尺寸
目录组织
访问延迟
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Summary:As more processing cores are integrated into one chip and feature size continues to shrink, the average access la- tency for remote nodes using directory-based coherence protocol becomes higher, which greatly impacts system performance. Previous techniques such as data replication and data migration optimize the performance of the requesting core, but offer little improvement for neighbor nodes. Other techniques such as in-transit optimization try to reduce latency at the cost of increased storage. This paper introduces hierarchical cache directory into CMP （chip multiprocessor）, which divides CMP tiles into multiple regions hierarchically, and combines it with data replication. A new directory organization is proposed to record the share status within a region and assist the regional home to complete operation efficiently. Simulation results show that for a 16-core CMP, compared to traditional directory, hierarchical cache directory reduces average access latency by 9% and on-chip network traffic by 34% on average with less storage. Theoretical analyses show that for a 2^n × 2^n tiled CMP, the average access latency in hierarchical cache directory asymptotically approaches a function that is independent of n, hence the architecture is highly scalable.
ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-010-9321-5