Hall and field-effect mobilities in few layered p-WSe₂ field-effect transistors

Here, we present a temperature (T) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe2 exfoliated onto SiO2. Without dielectric engineering and beyond a T-dependent threshold gate-voltage, we observe maximum hole mobilities approaching...

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Bibliographic Details
Published in:Scientific reports 2015-03, Vol.5 (1), p.8979-8979, Article 8979
Main Authors: Pradhan, N R, Rhodes, D, Memaran, S, Poumirol, J M, Smirnov, D, Talapatra, S, Feng, S, Perea-Lopez, N, Elias, A L, Terrones, M, Ajayan, P M, Balicas, L
Format: Article
Language:English
Subjects:
Capacitance
Localization
Temperature effects
Transistors
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Summary:Here, we present a temperature (T) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe2 exfoliated onto SiO2. Without dielectric engineering and beyond a T-dependent threshold gate-voltage, we observe maximum hole mobilities approaching 350 cm(2)/Vs at T = 300 K. The hole Hall mobility reaches a maximum value of 650 cm(2)/Vs as T is lowered below ~150 K, indicating that insofar WSe2-based field-effect transistors (FETs) display the largest Hall mobilities among the transition metal dichalcogenides. The gate capacitance, as extracted from the Hall-effect, reveals the presence of spurious charges in the channel, while the two-terminal sheet resistivity displays two-dimensional variable-range hopping behavior, indicating carrier localization induced by disorder at the interface between WSe2 and SiO2. We argue that improvements in the fabrication protocols as, for example, the use of a substrate free of dangling bonds are likely to produce WSe2-based FETs displaying higher room temperature mobilities, i.e. approaching those of p-doped Si, which would make it a suitable candidate for high performance opto-electronics.
ISSN:2045-2322
2045-2322
DOI:10.1038/srep08979