1000-V 9.1-[Formula Omitted] Normally Off 4H-SiC Lateral RESURF JFET for Power Integrated Circuit Applications

A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field- effect transistor (JFET) with a blocking voltage V@@dbr@ of 1028 V and a specific on-resistance R @@don-sp@ of 9.1 mOmegamiddotcm@@u2@ has been experimentally demonstrated. The device has a V@@dbr@...

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Bibliographic Details
Published in:IEEE electron device letters 2007-05, Vol.28 (5), p.404-407
Main Authors: Zhang, Yongxi, Sheng, Kuang, Su, Ming, Zhao, J H, Alexandrov, P, Fursin, L
Format: Article
Language:English
Subjects:
Aluminum
Channels
Devices
Electric potential
Electrical junctions
Implantation
JFET
Materials handling
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Summary:A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field- effect transistor (JFET) with a blocking voltage V@@dbr@ of 1028 V and a specific on-resistance R @@don-sp@ of 9.1 mOmegamiddotcm@@u2@ has been experimentally demonstrated. The device has a V@@dbr@ @@u2@/R@@don-sp@ figure-of-merit of 116 MW/cm@@u2@, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01times10@@u-3@ cm@@u2@. The fabricated double-RESURF devices have a vertical channel length of 1.8 mum, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift- region length of 7.5 mum. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2007.895448