2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.174-185
Main Authors: Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.
Format: Article
Language:English
Subjects:
2T cell
3T cell
Applied sciences
Bandwidth
Circuits
Clocks
Costs
Cycle time
Design. Technologies. Operation analysis. Testing
dram
eDRAM
Electric potential
Electronics
Engines
Exact sciences and technology
Gain
gain cell
Ground support
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic
memory
Microprocessors
Nondestructive testing
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Voltage
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Summary:We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2007155