Direct Formation of Wafer Scale Graphene Thin Layers on Insulating Substrates by Chemical Vapor Deposition

Direct formation of high-quality and wafer scale graphene thin layers on insulating gate dielectrics such as SiO2 is emergent for graphene electronics using Si-wafer compatible fabrication. Here, we report that in a chemical vapor deposition process the carbon species dissociated on Cu surfaces not...

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Bibliographic Details
Published in:Nano letters 2011-09, Vol.11 (9), p.3612-3616
Main Authors: Su, Ching-Yuan, Lu, Ang-Yu, Wu, Chih-Yu, Li, Yi-Te, Liu, Keng-Ku, Zhang, Wenjing, Lin, Shi-Yen, Juang, Zheng-Yu, Zhong, Yuan-Liang, Chen, Fu-Rong, Li, Lain-Jong
Format: Article
Language:English
Subjects:
Applied sciences
Chemical vapor deposition
Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.)
Copper
Cross-disciplinary physics: materials science
rheology
Dielectrics
Electronics
Exact sciences and technology
Formations
Fullerenes and related materials
diamonds, graphite
Graphene
Materials science
Methods of deposition of films and coatings
film growth and epitaxy
Molecular electronics, nanoelectronics
Nanostructure
Physics
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Specific materials
Thin films
Wafers
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Summary:Direct formation of high-quality and wafer scale graphene thin layers on insulating gate dielectrics such as SiO2 is emergent for graphene electronics using Si-wafer compatible fabrication. Here, we report that in a chemical vapor deposition process the carbon species dissociated on Cu surfaces not only result in graphene layers on top of the catalytic Cu thin films but also diffuse through Cu grain boundaries to the interface between Cu and underlying dielectrics. Optimization of the process parameters leads to a continuous and large-area graphene thin layers directly formed on top of the dielectrics. The bottom-gated transistor characteristics for the graphene films have shown quite comparable carrier mobility compared to the top-layer graphene. The proposed method allows us to achieve wafer-sized graphene on versatile insulating substrates without the need of graphene transfer.
ISSN:1530-6984
1530-6992
DOI:10.1021/nl201362n