On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects

This paper presents a comprehensive study of the applicability of single-walled carbon nanotubes (SWCNTs) as interconnects in nanoscale integrated circuits. A detailed analysis of SWCNT interconnect resistance (considering its dependence on all physical parameters, as well as factors affecting the c...

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Bibliographic Details
Published in:IEEE transactions on nanotechnology 2009-07, Vol.8 (4), p.542-559
Main Authors: Srivastava, N., Hong Li, Kreupl, F., Banerjee, K.
Format: Article
Language:English
Subjects:
Analytical models
Applied sciences
Bundles
Capacitance
Carbon
Carbon nanotube (CNT)
Carbon nanotubes
Circuit analysis
Circuit simulation
Contact resistance
Copper
Cross-disciplinary physics: materials science
rheology
Delay
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuit interconnections
Integrated circuits
Materials science
Nanoscale materials and structures: fabrication and characterization
Nanostructure
Nanotechnology
Nanotubes
Physics
power
Power dissipation
reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Single wall carbon nanotubes
thermal management
Very large scale integration
very large scale integration (VLSI) interconnect
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Summary:This paper presents a comprehensive study of the applicability of single-walled carbon nanotubes (SWCNTs) as interconnects in nanoscale integrated circuits. A detailed analysis of SWCNT interconnect resistance (considering its dependence on all physical parameters, as well as factors affecting the contact resistance), the first full 3-D capacitance simulations of SWCNT bundles for realistic very large scale integration (VLSI) interconnect dimensions, and a quantitative evaluation of the importance of inductive effects in SWCNT interconnects are presented. The applicability of carbon nanotube (CNT) based vias (vertical interconnects)-the most realizable CNT interconnects in the current state of the art-is addressed for the first time. It is shown that CNT interconnects can provide 30%-40% improvement in the delay of millimeter-long global interconnects. The applicability of CNT monolayers as local interconnects is found to be much more limited than that reported in the prior literature. Dense CNT bundle global interconnects are shown to offer a 4times reduction in power dissipation while achieving the same delay as optimally buffered Cu interconnects at the 22 nm node. This power saving increases to 8times at the 14 nm node. Furthermore, 3-D finite-element electrothermal simulations show that CNT bundles used as vias in between Cu metal layers can provide large improvement in metal interconnect lifetime by lowering the temperature of the hottest interconnects.
ISSN:1536-125X
1941-0085
DOI:10.1109/TNANO.2009.2013945