A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expecte...

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Bibliographic Details
Main Authors: Colwell, Robert P., Nix, Robert P., O'Donnell, John J., Papworth, David B., Rodman, Paul K.
Format: Conference Proceeding
Language:English
Subjects:
Computer systems organization > Architectures > Other architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
General and reference > Cross-computing tools and techniques > Performance
Networks > Network performance evaluation
Software and its engineering > Software notations and tools > Compilers
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Summary:Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACETM along with its companion Trace SchedulingTM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.
ISSN:0163-5964
DOI:10.1145/36206.36201