Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching . However, with atomically thin body t...

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Bibliographic Details
Published in:Nature (London) 2024-05, Vol.630 (8016), p.340-345N
Main Authors: Lu, Donglin, Chen, Yang, Lu, Zheyi, Ma, Likuan, Tao, Quanyang, Li, Zhiwei, Kong, Lingan, Liu, Liting, Yang, Xiaokun, Ding, Shuimei, Liu, Xiao, Li, Yunxin, Wu, Ruixia, Wang, Yiliu, Hu, Yuanyuan, Duan, Xidong, Liao, Lei, Liu, Yuan
Format: Article
Language:English
Subjects:
Electrical properties
Energy
Free surfaces
Integration
Laminating
Lamination
Low dimensional semiconductors
Low temperature
Plasma etching
Polymers
Polyvinyl alcohol
Semiconductors
Silicon wafers
Substrates
Thin bodies
Transistors
Two dimensional bodies
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Summary:Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching . However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics , where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.
ISSN:0028-0836
1476-4687
1476-4687
DOI:10.1038/s41586-024-07406-z