MaRs: a parallel graph reduction multiprocessor

We describe the MaRS machine: a parallel, distributed control multiprocessor for graph reduction using a functional machine language. The object code language is based on an optimized set of combinators, and its functional character allows an automatic parallelisation of the execution. A programming...

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Bibliographic Details
Published in:Computer architecture news 1988-06, Vol.16 (3), p.17-24
Main Authors: Castan, M., Contessa, A., Cousin, E., Coustet, C., Lecussan, B.
Format: Article
Language:English
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Summary:We describe the MaRS machine: a parallel, distributed control multiprocessor for graph reduction using a functional machine language. The object code language is based on an optimized set of combinators, and its functional character allows an automatic parallelisation of the execution. A programming language, "MaRS LISP", has also been developed. A prototype of MaRS is currently being designed in VLSI 1.5-micron CMOS technology with 2 levels of metal, by means of a CAD system. The machine uses three basic types of processors for Reduction, Memory and Communication, plus auxiliary I/O and Arithmetic Processors; communications do not constitute an operational bottleneck, as interprocessor messages are routed via an Omega switching network. Initially, a Host Computer will be used for startup, testing and direct memory access. The machine architecture and its functional organization are described, as well as the theoretical execution model. We conclude on a number of specialized hardware and software mechanism that differentiate MaRS machine from other similar projects currently going on.
ISSN:0163-5964
DOI:10.1145/48675.48678