A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current,...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1995-11, Vol.30 (11), p.1239-1245
Main Authors: Hanyu, T., Kameyama, M.
Format: Article
Language:English
Subjects:
Arithmetic
CMOS technology
Current mode circuits
Delay
Detectors
Logic circuits
Low voltage
Power dissipation
Switching circuits
Wiring
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Description
Summary:A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54/spl times/51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-/spl mu/m standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.475711