Scaling to the end of silicon with EDGE architectures

Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, ca...

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 2004-07, Vol.37 (7), p.44-55
Main Authors: Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C., Moore, C.R., Burrill, J., McDonald, R.G., Yoder, W.
Format: Article
Language:English
Subjects:
Acceleration
Clocks
CMOS technology
Computer architecture
Design engineering
Instruction sets
Microprocessors
Pipeline processing
Processor scheduling
Reduced instruction set computing
Silicon
VLIW
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Summary:Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, called explicit data graph execution (EDGE), that will match the characteristics of semiconductor technology over the next decade. The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
ISSN:0018-9162
1558-0814
DOI:10.1109/MC.2004.65