Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computatio...

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Bibliographic Details
Published in:IEEE transactions on signal processing 2003-02, Vol.51 (2), p.458-469
Main Authors: Hunsoo Choo, Muhammad, K., Roy, K.
Format: Article
Language:English
Subjects:
Adaptive filters
Applied sciences
Complement
Computation
Computer architecture
Decision feedback equalizers
Detection, estimation, filtering, equalization, prediction
Digital signal processing
Digital signal processors
Electronics
Energy consumption
Exact sciences and technology
Filtering
Finite impulse response filter
High performance computing
Impulse response
Information, signal and communications theory
Integrated circuits
Integrated circuits by function (including memories and processors)
Multipliers
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal and communications theory
Signal processing algorithms
Signal, noise
Telecommunications and information theory
Throughput
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Summary:We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.
ISSN:1053-587X
1941-0476
DOI:10.1109/TSP.2002.806984