Multifrequency zero-jitter delay-locked loop

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-01, Vol.29 (1), p.67-70
Main Authors: Efendovich, A., Afek, Y., Sella, C., Bikowsky, Z.
Format: Article
Language:English
Subjects:
Applied sciences
Central Processing Unit
Circuits
Clocks
Delay
Design. Technologies. Operation analysis. Testing
Detectors
Electronics
Exact sciences and technology
Frequency synchronization
Integrated circuits
Jitter
Master-slave
Phase detection
Phase locked loops
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.272097