Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the l...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1992-04, Vol.27 (4), p.473-484
Main Authors: Chandrakasan, A.P., Sheng, S., Brodersen, R.W.
Format: Article
Language:English
Subjects:
Applied sciences
CMOS digital integrated circuits
CMOS logic circuits
CMOS technology
Coupling circuits
Design. Technologies. Operation analysis. Testing
Digital circuits
Electronics
Energy consumption
Engineering
Engineering, Electrical & Electronic
Exact sciences and technology
Integrated circuits
Logic circuits
Portable computers
Science & Technology
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Technology
Throughput
Voltage
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Description
Summary:Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.126534