High-performance 1-Gb-NAND flash memory with 0.12-mum technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-mum CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 mum(2) and 129.6 mm(2), respectively....

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2002-11, Vol.37 (11), p.1502-1509
Main Authors: Lee, June, Im, Heung-Soo, Byeon, Dae-Seok, Lee, Kyeong-Han, Chae, Dong-Hyuk, Lee, Kyong-Hwa, Hwang, Sang Won, Lee, Sung-Soo, Lim, Young-Ho, Lee, Jae-Duk, Choi, Jung-Dal, Seo, Young-Il, Lee, Jong-Sik, Suh, Kang-Deog
Format: Article
Language:English
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Summary:A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-mum CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 mum(2) and 129.6 mm(2), respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/DD/ is obtained.
ISSN:0018-9200
DOI:10.1109/JSSC.2002.802352