Critical paths in circuits with level-sensitive latches

This paper extends the classical notion of critical paths in combinational circuits to the case of synchronous circuits that use level-sensitive latches. Critical paths in such circuits arise from setup, hold, and cyclic constraints on the data signals at the inputs of each latch and may extend thro...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 1995-06, Vol.3 (2), p.273-291
Main Authors: Burks, T.M., Sakallah, K.A., Mudge, T.N.
Format: Article
Language:English
Subjects:
Circuit analysis
Clocks
Combinational circuits
Latches
Microprocessors
Processor scheduling
Sequential circuits
Signal analysis
Timing
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Summary:This paper extends the classical notion of critical paths in combinational circuits to the case of synchronous circuits that use level-sensitive latches. Critical paths in such circuits arise from setup, hold, and cyclic constraints on the data signals at the inputs of each latch and may extend through one or more latches. Two approaches are presented for identifying these critical paths and verifying their timing. The first implicitly checks all paths using a relaxation-based solution procedure. Results of this procedure are used to calculate slack values, which in turn identify satisfied and violated critical paths. The second approach is based on a constructive algorithm which generates all the critical paths in a circuit and then verifies that their timing constraints are satisfied. Algorithms are evaluated and compared using circuits from the ISCAS89 sequential benchmark suite and the Michigan High Performance Microprocessor Project.< >
ISSN:1063-8210
1557-9999
DOI:10.1109/92.386227