A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3- mu m technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1991-11, Vol.26 (11), p.1530-1537
Main Authors: Kawahara, T., Kawajiri, Y., Kitsukawa, G., Nakagome, Y., Sagara, K., Kawamoto, Y., Akiba, T., Kato, S., Kawase, Y., Itoh, K.
Format: Article
Language:English
Subjects:
Applied sciences
BiCMOS integrated circuits
CMOS technology
Current supplies
Electronics
Exact sciences and technology
Fluctuations
Helium
Integrated circuits
Integrated circuits by function (including memories and processors)
Power amplifiers
Power supplies
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
System performance
Voltage
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Summary:The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3- mu m technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.98968