A 117-mm(2) 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multil...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1996-11, Vol.31 (11), p.1575-1583
Main Authors: Jung, Tae-Sung, Choi, Young-Joon, Suh, Kang-Deog, Suh, Byung-Hoon, Kim, Jin-Ki, Lim, Young-Ho, Koh, Yong-Nam, Park, Jong-Wook, Lee, Ki-Jong, Park, Jung-Hoon, Park, Kee-Tae, Kim, Jhang-Rae, Yi, Jeong-Hyong, Lim, Hyung-Kyu
Format: Article
Language:English
Online Access:Get full text
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Summary:For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-mum CMOS technology, resulting in a 117 mm(2) die size and a 1.1 mum(2) effective cell size
ISSN:0018-9200
DOI:10.1109/JSSC.1996.542301