Coplanar integration of lattice-mismatched semiconductors with silicon by wafer bonding Ge/Si1-xGex/Si virtual substrates

We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si1-xGex/Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identi...

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Bibliographic Details
Published in:Journal of the Electrochemical Society 2004, Vol.151 (7), p.G443-G447
Main Authors: PITERA, Arthur J, TARASCHI, G, LEE, M. L, LEITZ, C. W, CHENG, Z.-Y, FITZGERALD, E. A
Format: Article
Language:English
Subjects:
Applied sciences
Cross-disciplinary physics: materials science
rheology
Electronics
Exact sciences and technology
Materials science
Microelectronic fabrication (materials and surfaces technology)
Physics
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Surface treatments
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Summary:We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si1-xGex/Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial Ge/SiO2 to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using H2-induced layer exfoliation (SmartcutTM) and a buried Si0.4Ge0.6 etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of < 15 nm rms as measured on a 25 X 25 mm scale and a 1 X 1 mum scale roughness of < 1.4 nm. Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers.
ISSN:0013-4651
1945-7111
DOI:10.1149/1.1757462