A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two ti...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-05, Vol.40 (5), p.1057-1067
Main Authors: Limotyrakis, S., Kulchycki, S.D., Su, D.K., Wooley, B.A.
Format: Article
Language:English
Subjects:
Amplifiers
Analog-digital (A/D) conversion
Analog-digital conversion
Applied sciences
Circuit properties
Circuits
CMOS
CMOS analog integrated circuits
CMOS technology
comparators
Converters
Design. Technologies. Operation analysis. Testing
Dielectric, amorphous and glass solid devices
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
folding A/D converters
Frequency
High speed
Integrated circuits
mixed analog-digital integrated circuits
Noise levels
Operational amplifiers
pipeline processing
Pipelines
Power amplifiers
Power dissipation
Prototypes
Residues
Sampling
Sampling methods
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
switched-capacitor circuits
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Description
Summary:A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.845992