Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are construct...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2002-02, Vol.10 (1), p.20-29
Main Authors: Shams, A.M., Darwish, T.K., Bayoumi, M.A.
Format: Article
Language:English
Subjects:
Adders
Applied sciences
Arithmetic
Buildings
Circuit properties
Circuit simulation
Circuits
CMOS
Design engineering
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Joining
Joining processes
Modules
Performance analysis
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Switching circuits
Very large scale integration
Virtual prototyping
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Summary:A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.
ISSN:1063-8210
1557-9999
DOI:10.1109/92.988727