40Gb/s ASIC switch design using low-jitter clock recovery

A 40Gb/s application specific integrated circuit (ASIC) switch design is proposed using low-jitter clock recovery (LJCR). The main building blocks of the proposed switch fabric consists of data and overhead switch (DOS) ASIC. Each of these ASICs has 32 inputs and 32 outputs capable of working at 1.2...

Full description

Saved in:
Bibliographic Details
Main Authors: Pathak, V, Shaw, C-H, Vance, B, Devalapalli, S, Smith, P, Bonelli, A, Ribo, J, Bonte, O, Bauduin, F, Roderer, B, Verghese, M, Grant, I, Mah, H, Kean, C, Begin, P
Format: Conference Proceeding
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 40Gb/s application specific integrated circuit (ASIC) switch design is proposed using low-jitter clock recovery (LJCR). The main building blocks of the proposed switch fabric consists of data and overhead switch (DOS) ASIC. Each of these ASICs has 32 inputs and 32 outputs capable of working at 1.25Gb/s maximum data rate. The schematic diagram of the switch ASIC is described. This ASIC design uses a high-performance CMOS gate array technology with split transistors to construct core logic at 1.8 V and I/Os at 3.3 V.
ISSN:0193-6530