Low-voltage double-sampled sigma Delta converters

A simple method to solve degradation of signal-to-noise ratio (SNR) performance in double sampling in second-order sigma Delta analog-to-digital converter (ADC) uses internal decimation to relax the bandwidth requirements of the op-amps. Both circuitries must use a 1.5 supply voltage by using clock...

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Bibliographic Details
Main Authors: Senderowicz, Daniel, Nicollini, Germano, Pernici, Sergio, Nagari, Angelo, Confalonieri, Pierangelo, Dallavalle, Carlo
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:A simple method to solve degradation of signal-to-noise ratio (SNR) performance in double sampling in second-order sigma Delta analog-to-digital converter (ADC) uses internal decimation to relax the bandwidth requirements of the op-amps. Both circuitries must use a 1.5 supply voltage by using clock bootstrapping. The use of lower supply voltages and the need for enhanced power-supply mandates the use of fully differential architectures. In the digital-to-analog converter (DAC) structure, a digital sigma Delta loop acting as a final interpolating stage precedes the reconstruction filter hence, spurious modulation of the signal at the filter input should be avoided.
ISSN:0193-6530
DOI:10.1109/ISSCC.1997.585336