Memory Access Scheduling for a Smart TV

A smart TV system-on-chip (SoC) has very heavy computation and memory demands that must be met with low-cost components. As a result, there is potentially an extremely high utilization of the channel between the SoC and its memory chip. This paper presents the design of a new memory access scheduler...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2016-02, Vol.26 (2), p.399-411
Main Authors: Hahm, Cheul-Hee, Lee, Sunggu, Lee, Taeyoung, Yoo, Sungjoo
Format: Article
Language:English
Subjects:
Channels
Computer memory
Computer simulation
Demand
Driving conditions
Extreme values
memory access scheduler
Memory management
Real time
Real-time systems
Servers
smart TV
synchronous dynamic random access memory
System on chip
Television
Throughput
Timing
Traffic
Traffic engineering
Traffic flow
Upper bounds
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Summary:A smart TV system-on-chip (SoC) has very heavy computation and memory demands that must be met with low-cost components. As a result, there is potentially an extremely high utilization of the channel between the SoC and its memory chip. This paper presents the design of a new memory access scheduler customized for the type of memory traffic typically encountered with smart TVs. This includes special accumulated hard real-time graphics requirements, user response-sensitive soft real-time requirements, and the need to provide high memory throughput and priority-handling capabilities even under extremely heavy memory traffic conditions. The simulation results show that the proposed memory access scheduler is able to achieve up to 98% of the ideal upper bound memory throughput when faced with extremely heavy memory traffic-this is a significant improvement over previous schedulers. Novel future prediction and light-handed priority handling methods are used to achieve these results while satisfying the unique real-time requirements of smart TVs.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2015.2389414