An Agile Approach to Building RISC-V Microprocessors

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedu...

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Bibliographic Details
Published in:IEEE MICRO 2016-03, Vol.36 (2), p.8-20
Main Authors: Yunsup Lee, Waterman, Andrew, Cook, Henry, Zimmer, Brian, Keller, Ben, Puggelli, Alberto, Kwak, Jaehwa, Jevtic, Ruzica, Bailey, Stevo, Blagojevic, Milovan, Pi-Feng Chiu, Avizienis, Rimas, Richards, Brian, Bachrach, Jonathan, Patterson, David, Alon, Elad, Nikolic, Bora, Asanovic, Krste
Format: Article
Language:English
Subjects:
Agile software development
CMOS
CMOS integrated circuits
CMOS technology
Computer peripherals
computer system implementation
computer systems organization
Construction costs
Energy efficiency
Generators
Hand tools
Hardware
instruction set design
integrated circuits
Methodology
microcomputers
Microprocessors
Prototypes
Semiconductors
Software development
systems specification methodology
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Summary:The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2016.11