Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In...

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Bibliographic Details
Published in:IEEE electron device letters 2011-04, Vol.32 (4), p.521-523
Main Authors: Su, Chun-Jung, Tsai, Tzu-I, Liou, Yu-Ling, Lin, Zer-Ming, Lin, Horng-Chih, Chao, Tien-Sheng
Format: Article
Language:English
Subjects:
Accumulation mode
Channels
Devices
Drains
Fabrication
Feasibility
gate all around (GAA)
inversion mode (IM)
Logic gates
Materials
MOSFETs
Nanocomposites
Nanomaterials
Nanoscale devices
Nanostructure
nanowire (NW)
Nanowires
Performance evaluation
Semiconductor devices
thin-film transistor (TFT)
Transistors
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Summary:In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2011.2107498