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10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network

For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suit...

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Bibliographic Details
Published in:Journal of instrumentation 2013-12, Vol.8 (12), p.C12039-C12039
Main Authors: Bauer, G, Bawej, T, Behrens, U, Branson, J, Chaze, O, Cittolin, S, Coarasa, J A, Darlea, G -L, Deldicque, C, Dobson, M, Dupont, A, Erhan, S, Gigi, D, Glege, F, Gomez-Ceballos, G, Gomez-Reino, R, Hartl, C, Hegeman, J, Holzner, A, Masetti, L, Meijers, F, Meschi, E, Mommsen, R K, Morovic, S, Nunez-Barranco-Fernandez, C, O'Dell, V, Orsini, L, Ozga, W, Paus, C, Petrucci, A, Pieri, M, Racz, A, Raginel, O, Sakulin, H, Sani, M, Schwick, C, Spataru, A C, Stieger, B, Sumorok, K, Veverka, J, Wakefield, C C, Zejdl, P
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Language:English
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Summary:For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to TCP in order to simplify its FPGA implementation together with a set of performance measurements which were carried out with the current prototype.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/8/12/C12039