Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2014-10, Vol.22 (10), p.2238-2242
Main Authors: Nunez, Juan, Avedillo, Maria J., Quintana, Jose M.
Format: Article
Language:English
Subjects:
Circuits
Clock schemes
Clocks
CMOS
Devices
Gates (circuits)
Interconnection
Inverters
Logic gates
Mobile communication
monostable-to-bistable (MOBILE) logic element
negative differential resistance (NDR)
pipeline
Pipeline processing
Pipelines
Transistors
Very large scale integration
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Summary:Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2283306