A 1-v 2.5-mw 5.2-ghz frequency divider in a 0.35-μm cmos process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard d...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2003-10, Vol.38 (10), p.1643-1648
Main Authors: Wong, J.M.C., Cheung, V.S.L., Luong, H.C.
Format: Article
Language:English
Subjects:
Circuits
CMOS
Dividers
Flip-flops
Frequency dividers
High speed
Power consumption
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Summary:A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35- mu m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.
ISSN:0018-9200
DOI:10.1109/JSSC.2003.817261