Hierarchical circuit-switched NoC for multicore video processing

Today’s prevailing video systems demand extreme performance that can be efficiently supported by parallel computing engines. This paper presents a novel hierarchical circuit-switched ring network on chip (called HrNoC) for the parallel engines, of which the cost, power, and latency have been extensi...

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Bibliographic Details
Published in:Microprocessors and microsystems 2011-03, Vol.35 (2), p.182-199
Main Authors: Chou, Shu-Hsuan, Chen, Chien-Chih, Wen, Chi-Neng, Chen, Tien-Fu, Lin, Tay-Jyi
Format: Article
Language:English
Subjects:
Application mapping
Avoidance
Circuit-switching
Circuits
Cost engineering
Engines
Hierarchical architecture
Joints
Microprocessors
Network clustering
Network on chip
Packet-switching
Power consumption
Ring interconnections
Specifications
Streams
Video processing
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Summary:Today’s prevailing video systems demand extreme performance that can be efficiently supported by parallel computing engines. This paper presents a novel hierarchical circuit-switched ring network on chip (called HrNoC) for the parallel engines, of which the cost, power, and latency have been extensively optimized from bottom up. First, a communication scheme “wave” is proposed for both intra-ring and inter-ring routing-paths built with rapid stream transactions. Then, a cost-effective bridge featuring deterministic packet traversal and deadlock avoidance is designed for flexible inter-ring connections. Finally, varied configurations of hierarchical rings are exploited by system specification and application mapping. In experiments, the proposed HrNoC on a 16-core multicore system performs about 50% latency reduction, 1/3 area cost, and 1/5 power consumption, compared with a packet-switched mesh NoC.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2010.09.009