Stress analyses of high spatial resolution on TSV and BEoL structures

Knowledge and control of local stress development in Back-End-of-Line (BEoL) stacks and nearby Through Silicon Vias (TSVs) in advanced 3D integrated devices is a key to their thermo-mechanical reliability. The paper presents a combined simulation/measurement approach to evaluate stresses generated i...

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Bibliographic Details
Published in:Microelectronics and reliability 2014-09, Vol.54 (9-10), p.1963-1968
Main Authors: Vogel, D., Auerswald, E., Auersperg, J., Bayat, P., Rodriguez, R.D., Zahn, D.R.T., Rzepka, S., Michel, B.
Format: Article
Language:English
Subjects:
Applied sciences
BEoL
Design. Technologies. Operation analysis. Testing
Digital Image Correlation
Electronics
Exact sciences and technology
Finite Element Analysis
Finite element method
Integrated circuits
Microelectronic fabrication (materials and surfaces technology)
MicroRaman
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Spatial resolution
Stacks
Stress
Stress measurement
Stresses
Three dimensional
TSV
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Summary:Knowledge and control of local stress development in Back-End-of-Line (BEoL) stacks and nearby Through Silicon Vias (TSVs) in advanced 3D integrated devices is a key to their thermo-mechanical reliability. The paper presents a combined simulation/measurement approach to evaluate stresses generated in the result of the TSV and BEoL stack manufacturing and 3D bonding processes. Stress measurement methods of high spatial resolution capability (microRaman and Focused Ion Beam (FIB) based stress release techniques) are used to obtain stress data from real components as manufactured. Finite Element Analysis (FEA) allows a more accurate interpretation of measurements results as well as a subsequent comprehensive analysis of failure behaviour. The paper gives an introduction to the applied local stress measurement on advanced multi-layer systems and 3D integration components referring to the state-of-art capabilities and limitations. The need of experimental stress data generation is illustrated on FEA examples. Illustration is given for FEA applications on 3D IC integration components currently lacking appropriate residual stress input for an assumed initial state.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2014.07.098