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Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm
In this work we experimentally demonstrate a novel method to fabricate short channel complementary planar strained Si (sSOI) TFETs with improved tunneling junctions by implantation into silicide method (IIS). For the first time we have successfully fabricated both, n- and p-type TFETs with high on-c...
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Published in: | Solid-state electronics 2014-07, Vol.97, p.76-81 |
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Main Authors: | , , , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Online Access: | Get full text |
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Summary: | In this work we experimentally demonstrate a novel method to fabricate short channel complementary planar strained Si (sSOI) TFETs with improved tunneling junctions by implantation into silicide method (IIS). For the first time we have successfully fabricated both, n- and p-type TFETs with high on-currents using ultra thin sSOI structures. We demonstrate all Si complementary TFET (C-TFET) inverters with a gain as large as 60 at V sub(DD) = 2 V and sharp transitions down to very low V sub(DD) = 0.2 V. The first transient response analysis of the NW C-TFET inverter showed a propagation delay of t sub(p) < 20 ns for L sub(G) = 50 nm. Nanowire array devices with improved electrostatic control compared to a planar device geometry with 15 nm wires were fabricated using Si sub(1) sub(-) sub(x)Ge sub(x) with x = 35% and x = 50% showing improved I sub(ON) with increasing Ge concentration. As compared to SiGe homojunction devices, Si sub(1) sub(-) sub(x)Ge sub(x)/Si heterostructure NW TFETs show improved I sub(ON)/I sub(OFF) ratio up to 8 orders of magnitude and reduced trap assisted tunnelling (TAT) due to in situ source doping. |
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ISSN: | 0038-1101 1879-2405 |
DOI: | 10.1016/j.sse.2014.04.025 |