UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

► GP introduction has only marginal effect on UTBB MOSFET analog FoM (slightly higher body factor in devices with GP).► ADG (i.e. front- to back-gate shorten) allows improved gate-to-channel coupling and SCE control (DIBL, S, VTh roll-off).► ADG bring about 20% improvement of analog FoM (such as gm,...

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Bibliographic Details
Published in:Solid-state electronics 2013-12, Vol.90, p.56-64
Main Authors: Md Arshad, M.K., Makovejev, S., Olsen, S., Andrieu, F., Raskin, J.-P., Flandre, D., Kilchytska, V.
Format: Article
Language:English
Subjects:
Analog figures of merit
Applied sciences
Asymmetrical double gate
Asymmetry
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Ground plane (GP) implementation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
Ultra-thin body and thin buried oxide FD SOI MOSFETs
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Summary:► GP introduction has only marginal effect on UTBB MOSFET analog FoM (slightly higher body factor in devices with GP).► ADG (i.e. front- to back-gate shorten) allows improved gate-to-channel coupling and SCE control (DIBL, S, VTh roll-off).► ADG bring about 20% improvement of analog FoM (such as gm, Id and intrinsic gain) in short-channel UTBB MOSFETs with GP.► Simulations predict that improvements of analog FoM provided by ADG are assured in the whole dynamic operation range.► ADG allows elimination of the high-frequency substrate coupling effect, thus improving intrinsic gain at high frequency. In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2013.02.051