An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator

This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed throug...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2004-05, Vol.51 (5), p.254-256
Main Authors: Kong-pang Pun, Chiu-sing Choy, Cheong-Fat Chan, da Franca, J.E.
Format: Article
Language:English
Subjects:
Analog-digital conversion
Capacitors
Dynamic range
Energy consumption
Feedback
Filtering theory
Frequency
Mixers
Sampling methods
Time sharing computer systems
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Summary:This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed through time sharing of the critical capacitors, i.e., the input sampling capacitor and the capacitor of the feedback digital-to-analog converter, between the I and Q channels. Circuit simulations verifying the proposed technique are presented.
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2004.827552