Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel l...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2009-04, Vol.56 (2), p.388-393
Main Authors: Arutinov, D., Barbero, M., Beccherle, R., Buscher, V., Darbo, G., Ely, R., Fougeron, D., Garcia-Sciveres, M., Gnani, D., Hemperek, T., Karagounis, M., Kluit, R., Kostyukhin, V., Mekkaoui, A., Menouni, M., Schipper, J.D., Wermes, N.
Format: Article
Language:eng
Subjects:
Architecture
Buffer storage
Chips
Colliding beam devices
Detectors
Digital
Digital integrated circuits
Drains
Electronics
Engineering Sciences
FE-I4
front end electronics
High Energy Physics - Experiment
Integrated circuit technology
Integrated circuits
Iron
Large Hadron Collider
Logic
Luminosity
Memory
Physics
pixel detectors
pixel electronics
Pixels
Springs
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Summary:A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.
ISSN:0018-9499
1558-1578