Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping

High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported prev...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2004-12, Vol.51 (12), p.2223-2228
Main Authors: Hardikar, S., Tadikonda, R., Green, D.W., Vershinin, K.V., Narayanan, E.M.S.
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
High-voltage integrated circuits (HVIC)
Integrated circuits
junction isolation
lateral diffused metal-oxide semiconductor (LDMOS)
MOSFETs
power ICs
Power integrated circuits
reduced surface field (RESURF)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
variation in lateral doping (VLD)
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Summary:High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2004.839104