Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the co...

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Bibliographic Details
Published in:IEEE journal of quantum electronics 2005-07, Vol.41 (7), p.1024-1036
Main Authors: Walker, A.C., Fancey, S.J., Desmulliez, M.P.Y., Forbes, M.G., Casswell, J.J., Buller, G.S., Taghizadeh, M.R., Dines, J.A.B., Stanley, C.R., Pennelli, G., Boyd, A.R., Pearson, J.L., Horan, P., Byrne, D., Hegarty, J., Eitel, S., Gauggel, H.-P., Gulden, K.-H., Gauthier, A., Benabes, P., Gutzwiller, J.-L., Goetz, M., Oksman, J.
Format: Article
Language:English
Subjects:
Aggregates
Applied sciences
Assembly
Assembly systems
Chips
Circuit properties
Circuit testing
CMOS
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Integrated optics. Optical fibers and wave guides
Interconnects, including holographic interconnects
Joints
OE-VLSI
Optical and optoelectronic circuits
Optical design
Optical devices
Optical interconnections
optical interconnects
Optical switches
Optoelectronic device characterization, design, and modeling
Optoelectronic devices
Optoelectronics
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
smart-pixels
Switches
System testing
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Description
Summary:The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 /spl times/ 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.
ISSN:0018-9197
1558-1713
DOI:10.1109/JQE.2005.848909