A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction

This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an...

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Bibliographic Details
Published in:IEEE open journal of circuits and systems 2024, Vol.5, p.291-301
Main Authors: Huang, Yu-Ping, Lu, Yu-Sian, Chen, Wei-Zen
Format: Article
Language:English
Subjects:
active cycle-jitter correction (ACJC)
Band-pass filters
Delays
Jitter
Noise
Phase frequency detectors
Phase locked loops
Sampling-based PD (SPD)
sub-sampling PD (SSPD)
Vibration
Voltage-controlled oscillators
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Summary:This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2.
ISSN:2644-1225
2644-1225
DOI:10.1109/OJCAS.2024.3416397