AxRSU-2m: Higher-Order m-Bit Approximate Encoders for Radix-2m Squarer Units

Approximate computing has emerged as a design alternative to enhance design efficiency by capitalizing on the inherent error resilience observed in numerous applications. Various error-resilient and compute-intensive applications, such as signal, image and video processing, computer vision, and supe...

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Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2024-06, Vol.43 (6), p.3649-3678
Main Authors: da Rosa, Morgana M. A., Paim, Guilherme, da Costa, Eduardo A. C., Soares, Rafael, Bampi, Sergio
Format: Article
Language:English
Subjects:
Accuracy
Approximation
Case studies
Circuits
Circuits and Systems
Coders
Computer vision
Design optimization
Electrical Engineering
Electronics and Microelectronics
Embedded systems
Energy consumption
Energy efficiency
Engineering
Errors
Hardware
Image processing
Instrumentation
Machine learning
Resilience
Signal processing
Signal,Image and Speech Processing
Supervised learning
Video
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Summary:Approximate computing has emerged as a design alternative to enhance design efficiency by capitalizing on the inherent error resilience observed in numerous applications. Various error-resilient and compute-intensive applications, such as signal, image and video processing, computer vision, and supervised machine learning, necessitate dedicated hardware accelerators for mean squared error estimation during runtime. In these application domains, using efficient arithmetic operators, particularly a squarer unit, represents one of the most effective strategies for low-power design. This work introduces an approximate Radix- 2 m squarer unit, denoted as AxRSU- 2 m . The proposed squarer unit employs m -bit approximate encoders to execute operations on m -bit data concurrently. The AxRSU- 2 m under consideration explores encoders with m equal to 2 (AxRSU-4), 3 (AxRSU-8), and 4 (AxRSU-16). These approximate encoders exhibit low complexity and diminish the necessary partial products operating on m bits simultaneously, thereby substantially enhancing energy efficiency and reducing circuit area in the AxRSU- 2 m . To illustrate the trade-off between error and quality in the AxRSU- 2 m , we apply it to an SSD (sum squared difference) hardware accelerator designed for video processing, with a square-accumulate serving as a case study. Our findings reveal a novel Pareto front, presenting eight optimal AxRSU- 2 m solutions that achieve accuracy levels ranging from 3.76 to 75.53%. These solutions yield energy savings ranging from 46.20 to 95.57% and circuit area reductions ranging from 37.68 to 66.73%.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-024-02616-2