AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems

Nowadays, system-on-chips have become critical since they support more and more safe applications due to their flexibility. However, they are susceptible to single-event upsets because the memory cell size has significantly shrunk. This article presents a triple redundant on-chip interconnect bus th...

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Bibliographic Details
Published in:IEEE transactions on reliability 2024-03, Vol.73 (1), p.1-6
Main Authors: Lazaro, Jesus, Astarloa, Armando, Zuloaga, Aitzol, Araujo, Jose Angel, Jimenez, Jaime
Format: Article
Language:English
Subjects:
AXI
Bus interconnections
Computer architecture
Field programmable gate arrays
FPGA
IP networks
Low speed
Microprocessors
Power consumption
Redundancy
Reliability
Single event upsets
SoC
Software
System on chip
System reliability
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Summary:Nowadays, system-on-chips have become critical since they support more and more safe applications due to their flexibility. However, they are susceptible to single-event upsets because the memory cell size has significantly shrunk. This article presents a triple redundant on-chip interconnect bus that provides low-speed peripherals with high reliability. In addition to correcting single errors and detecting duplicated ones, the proposed circuit offers zero latency and is transparent for both the embedded processor and the peripherals. These characteristics make it suitable for hard real-time applications. At the same time, the impact on area and power consumption is minimal.
ISSN:0018-9529
1558-1721
DOI:10.1109/TR.2023.3267436