GAAFET based SRAM Cell to Enhance Stability for Low Power Applications

This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6 T and 7 T SRAM cells on enhancing stability for low power applications. GAAFETs are used in cross-coupled inverter circuitry to increase the stability of proposed 6 T and 7 T SRAM cells as these cross-c...

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Bibliographic Details
Published in:SILICON 2022-08, Vol.14 (13), p.8161-8172
Main Authors: Kumar, Amit, Pattanaik, Manisha, Srivastava, Pankaj, Rajput, Anil Kumar
Format: Article
Language:English
Subjects:
Chemistry
Chemistry and Materials Science
Circuit design
Co-design
Delay
Design
Energy efficiency
Environmental Chemistry
Inorganic Chemistry
Internet of Things
Inverters
Lasers
Lookup tables
Materials Science
Optical Devices
Optics
Original Paper
Performance measurement
Photonics
Polymer Sciences
Power consumption
Power management
Silicon
Simulation
Stability
Static random access memory
Transistors
Trends
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Summary:This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6 T and 7 T SRAM cells on enhancing stability for low power applications. GAAFETs are used in cross-coupled inverter circuitry to increase the stability of proposed 6 T and 7 T SRAM cells as these cross-coupled inverters provide the closest ideal voltage transfer characteristics (VTC) due to the earlier saturation effect. The calibration of the simulation setup has also been done in this paper before using GAAFET in SRAM cell design. Moreover, the Look-up table-based Verilog A approach is adopted in the paper for device circuit co-design. Proposed 6 T SRAM cell is analysed for the performance metrics like read static noise margin (RSNM), write margin (WM), read delay, write delay, read power and write power at various supply voltages (V DD ) and further be improved to the proposed 7 T SRAM cell. The proposed 7 T SRAM enhances RSNM and WM by 55.56% and 24.60%, respectively, and also reduces read and write power consumption by 6.50% and 88.76%, respectively, as compared to DP-DGTFET based 7 T SRAM cell at V DD  = 0.6 V. Furthermore, proposed 7 T SRAM reduces read and write delay by 62.95% and 74.93% respectively at V DD  = 0.6 V as well. The power gating technique is used in the proposed 7 T SRAM to reduce leakage power by 37.18%, and 80.81% compared to the 6 T CMOS SRAM and proposed GAAFET based 6 T SRAM cell, respectively. Therefore, the proposed 7 T SRAM cell could be used for high stability and low power applications.
ISSN:1876-990X
1876-9918
DOI:10.1007/s12633-021-01580-9