Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding

The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as high-efficiency video coding (HEVC). SAD hardware architectures employ an adder tree to accumulate the coefficients from the absolute differe...

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Bibliographic Details
Published in:Journal of real-time image processing 2020-10, Vol.17 (5), p.1735-1754
Main Authors: Paim, Guilherme, Santana, Gustavo M., Abreu, Brunno A., Rocha, Leandro M. G., Grellert, Mateus, da Costa, Eduardo A. C., Bampi, Sergio
Format: Article
Language:English
Subjects:
Adding circuits
Coding
Coding standards
Compressors
Computer Graphics
Computer Science
Data processing
Design
Efficiency
Energy dissipation
Frames per second
Hardware
High definition
Image Processing and Computer Vision
Logic synthesis
Multimedia Information Systems
Original Research Paper
Pattern Recognition
Real time
Signal,Image and Speech Processing
Software
Sums
Video compression
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Summary:The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as high-efficiency video coding (HEVC). SAD hardware architectures employ an adder tree to accumulate the coefficients from the absolute difference between two video blocks. This paper employs high-order adder compressors (HOAC) structures into SAD hardware architectures to achieve ultra-high definition (UHD) encoding in real time, using block sizes compatible with HEVC. The proposed HOAC architectures are power-efficient and enable low-power SAD hardware accelerators. Our throughput analysis shows that the HOAC-based SAD hardware architecture is capable of encoding UHD 4K ( 3840 × 2160 ) videos in real-time at 60 frames per second. The architectures were entirely designed as dedicated ASIC blocks and were synthesized to ST 65 nm CMOS standard cells. Synthesis results show that SAD architectures using 64-2, 32-2, 16-2 and 8-2 compressors built from 4-2 compressors are significantly more efficient in terms of circuit area and total power dissipation when compared with SAD architectures using conventional adders selected by a commercial logic synthesis tool.
ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-019-00939-x