FPGA implementation of improved 32-bit wallace multiplier

VLSI design focuses on four primary design factors: area, power, speed, and cost. Standard multipliers have a higher number of different operations, which causes an increase in delay. As a result, circuits using conventional multipliers will be more power-hungry and slower. Digital signal processing...

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Bibliographic Details
Main Authors: Jami, Venkata Suman, Mani, Anitha Priyadarshini Ganduluru, Mamidipaka, Hema
Format: Conference Proceeding
Language:English
Subjects:
Design factors
Digital signal processing
Field programmable gate arrays
Multipliers
Online Access:Get full text
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Summary:VLSI design focuses on four primary design factors: area, power, speed, and cost. Standard multipliers have a higher number of different operations, which causes an increase in delay. As a result, circuits using conventional multipliers will be more power-hungry and slower. Digital signal processing relies heavily on multipliers. 32-bit enhanced Wallace multiplier design and FPGA implementation are presented in this study. Verilog HDL was used to code the proposed multiplier, and Xilinx Vivado simulated and synthesized it. It was then implemented on a Zynq 7000 series FPGA board.
ISSN:0094-243X
1551-7616
DOI:10.1063/5.0182119