An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

In this study, a low-power through-silicon via (TSV) I/O employing a low supply voltage (V_{\rm DDL}) for low-power operation with a 65-nm complementary metal-oxide-semiconductor (CMOS) process is proposed for high-bandwidth memory (HBM). The proposed TSV I/O satisfies the following requirements f...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2023-11, Vol.58 (11), p.1-11
Main Authors: Kim, Ji-Young, Kim, Taeryeong, You, Jeonghyeok, Kim, Kiryong, Moon, Byoung Mo, Sohn, Kyomin, Jung, Seong-Ook
Format: Article
Language:English
Subjects:
Bandwidth
Capacitance
CMOS
Delays
Electric potential
Energy efficiency
High-bandwidth memory (HBM) interface
Integrated circuits
Interconnections
low-power memory interface
low-supply voltage operation
low-swing single-ended through-silicon via (TSV) I/O
Power consumption
Power demand
Pseudorandom binary sequences
Signal integrity
Slew rate
Through-silicon vias
Transceivers
TSV
Voltage
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Summary:In this study, a low-power through-silicon via (TSV) I/O employing a low supply voltage (V_{\rm DDL}) for low-power operation with a 65-nm complementary metal-oxide-semiconductor (CMOS) process is proposed for high-bandwidth memory (HBM). The proposed TSV I/O satisfies the following requirements for implementing HBM I/O: a sufficient voltage margin of the transmitted signal, no static power consumption, and a small area overhead. For the improvement of the signal integrity (SI) under (V_{\rm DDL}) operation while satisfying the above requirements, a pre-driver with a main driver that enhances the slew rate of the transmitted signal and mitigates the impact of the process, voltage, and temperature (PVT) variations is proposed in the transmitter (TX). The proposed 1-to-4 demultiplexed comparator in the receiver (RX) does not use analog reference voltage for reducing area overhead. A simple reference calibrator is implemented in the RX to compensate for the input offset voltage and maximize the voltage and timing margin under PVT variations. An eight-stacked TSV is emulated and fabricated with six metal layers in the 65-nm CMOS process. The measured energy efficiency is 0.179-0.185 pJ/b/pF with a pseudorandom binary sequence (PRBS) of 31 at 5-10 Gb/s.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3285896