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Vertically Extended Channel Architecture for Implementing a Photolithographically Scalable Thin-Film Transistor
We present a prototype of photolithographically patternable thin-film transistor (TFT) architecture using vertically extended channel (VEC) for ultrahigh-resolution (UHR) display applications such as augmented reality and virtual reality (AR/VR) devices. Implementing UHR displays requires a unit pix...
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Published in: | IEEE electron device letters 2023-08, Vol.44 (8), p.1-1 |
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Main Authors: | , , , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites |
Online Access: | Get full text |
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Summary: | We present a prototype of photolithographically patternable thin-film transistor (TFT) architecture using vertically extended channel (VEC) for ultrahigh-resolution (UHR) display applications such as augmented reality and virtual reality (AR/VR) devices. Implementing UHR displays requires a unit pixel size of a few micrometers in pitch, so TFT footprints should be smaller than those of conventional planar structures, while retaining the appropriate on-current level and mobility. The proposed device has a small footprint of 4.5 F 2 compared to other TFT structures and can achieve higher mobility and on-current by increasing VEC thickness without changing any device channel feature size and footprint. The presented VEC TFT showed high saturation mobility of 22.4 cm 2 /V∙s and a linear increase in output characteristics as a function of VEC thickness variation. Furthermore, we demonstrated the back-end-of-line (BEOL) competitiveness of this device structure through the electrical parameter comparison among the planar TFT device structures, which were fabricated with a similar channel dimension. |
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ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2023.3286100 |