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Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication
This article presents two dual-photodiode (PD) differential optical receivers that achieve double photodetection area to support gigabit-per-second optical wireless communication (OWC), while maintaining the receiver bandwidth. To enable differential light detection with a single incident light beam...
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Published in: | IEEE journal of solid-state circuits 2023-06, Vol.58 (6), p.1681-1692 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | This article presents two dual-photodiode (PD) differential optical receivers that achieve double photodetection area to support gigabit-per-second optical wireless communication (OWC), while maintaining the receiver bandwidth. To enable differential light detection with a single incident light beam, a dual-PD OWC receiver architecture is proposed. In this architecture, two PDs are connected to the receiver complementarily without sacrificing the receiver bandwidth, and meanwhile, remain properly reversely biased. In addition, an adaptive dc photocurrent cancellation (ADPC) circuit is employed to prevent the saturation of the receivers under strong and imbalanced incident light. Based on the proposed architecture, two OWC receivers are implemented, including a proposed receiver and a reference one. In the proposed receiver, a low-noise shunt-feedback transimpedance amplifier (SF-TIA) with differential-pair-based current reuse and cross-coupled resistive feedback is proposed to enhance the sensitivity. In contrast, the reference receiver employs positive capacitive feedback to improve the transimpedance amplifier (TIA) performance. Both receivers have been fabricated with a standard 180 nm CMOS process and have been wire-bonded to two PDs. Experimental results indicate that both receivers can detect optical signals with data rates up to 2 Gb/s, and the proposed receiver architecture has significantly improved the bit error rate (BER) at 1.5 Gb/s from worse than 10^{-6} - 10^{-9} (error-free) with constrained optical power density. Moreover, the proposed receiver achieves an input sensitivity of 3.4~\mu \text{A}_{\mathrm {pp}} due to the superior performance of the proposed TIA, which outperforms the sensitivity of 10.4~\mu \text{A}_{\mathrm {pp}} from the reference receiver. Both sensitivities are measured at 1.5 Gb/s for a BER of 10^{-9} (error-free). The power consumption of the proposed and the reference receiver are 24.3 and 19.1 mW, respectively, excluding the output driver. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2023.3247950 |