A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices

This work proposes a 2-dimensional programable SRAM-based PUF. The selection of challenge groups, orders, and sequence lengths dominates the responses with challenge-response pairs (CRPs) by order of rows ^{\mathrm {(sequence~\textrm {}length- 1)}} \times columns ^{\mathrm {(sequence~\textrm {}leng...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-06, Vol.69 (6), p.2542-2552
Main Authors: Lu, Lu, Yoo, Taegeun, Kim, Tony Tae-Hyoung
Format: Article
Language:English
Subjects:
Bit error rate
challenge-response pairs
Hardware
hardware security
Inverters
Layout
Portable equipment
PUF
Random access memory
Reliability
Security
sequence-dependent
SRAM
Static random access memory
Transistors
two-dimension
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Summary:This work proposes a 2-dimensional programable SRAM-based PUF. The selection of challenge groups, orders, and sequence lengths dominates the responses with challenge-response pairs (CRPs) by order of rows ^{\mathrm {(sequence~\textrm {}length- 1)}} \times columns ^{\mathrm {(sequence~\textrm {}length - 1)}} . The PUF bit cell has split word-lines with vertical and horizontal connections, the bit-lines are placed orthogonally to generate one-bit data with four cells, the entropy source is enriched to 24 transistors. The proposed PUF supports multiple data maps from a single chip. A test chip was fabricated in 65 nm CMOS technology. Under 0.8V and 20 °C (nominal point), the bit error rate reaches 3%. In a single chip, the hamming distance achieves 42.49% within the same group and different orders of challenges, and 47.32% within the different groups of challenges (when the sequence length is 5). The measured inter-hamming distance between chips is improved to 49.47%.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3156983